In pulsed logic, such as Self-Resetting CMOS (SRCMOS) logic as described in copending and commonly assigned U.S. patent application Ser. No. 08/463,146, filed Jun. 5, 1995 incorporated herein by reference (hereinafter ("Chappell"), data (logical 0's or 1's) are represented by pulses, or the absence of pulses, on a given net, rather than as voltage levels as in other logic families. To implement sequential logic, these pulses must be launched from and captured into registers.
Since, in practice, however, chips using SRCMOS will also have static and possibly domino-type logic, a modular register approach that can be adapted to all of these logic types poses advantages. Such a register must, however, comply with and implement the circuit-level test modes described in commonly owned and copending U.S. patent application Ser. No. 08/583,300, entitled "Methodology to test pulsed logic circuits in pseudo-static mode", by M. P. Beakes et al., filed concurrently herewith, and incorporated herein by reference.
In particular, SRCMOS logic can be tested by a test mode called the "static evaluate mode". In this mode, resets are inhibited, by a global signal, "Evaluate", being active. At the same time, a recovery mechanism is activated to recover from false switching events (noise, glitches) such as might occur in mistimed chips. This recovery mechanism uses small leakage pFETs, switched on by another global signal, called "Static.sub.-- Evaluate". These leakage pFETs weakly pull up unidirectional switching nodes, effectively converting such unidirectional circuits to pseudo-nMOS circuits. See N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective, Addison Wesley, Reading Mass., 1988.
A further requirement of the register is that it comply with the Level Sensitive Scan Design methodology. In the LSSD testing methodology, a single-cycle AC performance test is defined. In this test, data is scanned into the registers, a single functional cycle is executed, and the resulting data is scanned out of the registers. Since pulsed logic is used in very high speed chips, single-cycle AC performance testing requires that the Scan.sub.-- Enable signal (the global signal that indicates whether the chip is in scan mode or in the (single cycle) functional mode) is synchronized to the system clock, without incurring the cost of a high speed precision distribution network.
Whenever preservation of register state over many machine cycles is required, a static register based on transmission gate inputs is advantageous. Such a register will hold state when none of its input ports is selected, without dissipating power associated with the input port multiplexer. Power dissipation in the holding state should be minimal.
However, transmission gate register structures are sensitive to false switching events on their Select lines, which may cause false data to be written. This can happen in a mis-timed chip in cycles where these false data are not subsequently overwritten by correct data. That is, in "hold" cycles where none of the input gates was supposed to be activated. The pseudo-nMOS type recovery mechanism of unidirectional switching nodes in static evaluate test mode, is not applicable to transmission gate type registers.